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SN74CB3Q3257 4 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER 2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH BUS SWITCH
SCDS135A - SEPTEMBER 2003 - REVISED NOVEMBER 2003
D High-Bandwidth Data Path D D D D D D
(Up to 500 MHz) 5-V Tolerant I/Os with Device Powered-Up or Powered-Down Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4 Typical) Rail-to-Rail Switching on Data I/O Ports - 0- to 5-V Switching With 3.3-V VCC - 0- to 3.3-V Switching With 2.5-V VCC Bidirectional Data Flow, With Near-Zero Propagation Delay Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical) Fast Switching Frequency (fOE = 20 MHz Max)
D Data and Control Inputs Provide D D D D D D D
Undershoot Clamp Diodes Low Power Consumption (ICC = 0.7 mA Typical) VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-B, Class II) - 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-Distortion Signal Gating
RGY PACKAGE (TOP VIEW)
For additional information regarding the performance characteristics of the CB3Q family, refer to the TI application report, CBT-C, CB3T, and CB3Q Signal-Switch Families, literature number SCDA008.
D
DBQ, DGV, OR PW PACKAGE (TOP VIEW)
S 1B1 1B2 1A 2B1 2B2 2A GND
2 3 4 5 6 7 8
15 14 13 12 11 10 9
1
S
1
16
VCC OE 4B1 4B2 4A 3B1 3B2 3A
16 15 OE 14 4B1 13 4B2 12 4A 11 3B1 10 3B2
1B1 1B2 1A 2B1 2B2 2A
2 3 4 5 6 7 8 9
description/ordering information
ORDERING INFORMATION
TA QFN - RGY SSOP (QSOP) - DBQ -40C to 85C TSSOP - PW TVSOP - DGV PACKAGE Tape and reel Tape and reel Tape and reel Tape and reel ORDERABLE PART NUMBER SN74CB3Q3257RGYR SN74CB3Q3257DBQR SN74CB3Q3257PWR SN74CB3Q3257DGVR TOP-SIDE MARKING BU257 BU257 BU257 BU257
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
GND
Copyright 2003, Texas Instruments Incorporated
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3A
VCC
1
SCDS135A - SEPTEMBER 2003 - REVISED NOVEMBER 2003
SN74CB3Q3257 4 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER 2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH BUS SWITCH
description/ordering information (continued)
The SN74CB3Q3257 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3257 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems. The SN74CB3Q3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer with a single output-enable (OE) input. The select (S) input controls the data path of the multiplexer/demultiplexer. When OE is low, the multiplexer/demultiplexer is enabled and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the multiplexer/demultiplexer is disabled and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered-down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE INPUTS OE L L H S L H X INPUT/OUTPUT A B1 B2 Z FUNCTION A port = B1 port A port = B2 port Disconnect
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SN74CB3Q3257 4 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER 2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH BUS SWITCH
SCDS135A - SEPTEMBER 2003 - REVISED NOVEMBER 2003
logic diagram (positive logic)
4 1A SW 3 SW 7 2A SW 6 SW 9 SW 10 SW 12 4A SW 13 SW 4B2 14 4B1 3B2 11 2B2 5 2B1 1B2 2 1B1
3A
3B1
1 S
15 OE
simplified schematic, each FET switch (SW)
A VCC B
Charge Pump
EN EN is the internal enable signal applied to the switch.
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3
SCDS135A - SEPTEMBER 2003 - REVISED NOVEMBER 2003
SN74CB3Q3257 4 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER 2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH BUS SWITCH
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA ON-state switch current, IIO (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 5): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W (see Note 5): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W (see Note 5): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90C/W (see Note 5): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W (see Note 5): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W (see Note 6): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. 6. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 7)
MIN VCC VIH VIL VI/O TA Supply voltage High-level control input voltage Low-level control input voltage Data input/output voltage Operating free-air temperature VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2.3 1.7 2 0 0 0 -40 MAX 3.6 5.5 5.5 0.7 0.8 5.5 85 V V C V UNIT V
NOTE 7: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SN74CB3Q3257 4 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER 2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH BUS SWITCH
SCDS135A - SEPTEMBER 2003 - REVISED NOVEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK IIN IOZ Ioff ICC ICC ICCD Cin Control inputs Per control input Control inputs A port Cio(OFF) B port A port Cio(ON) B port VCC = 3.3 V, VCC = 2.3 V, TYP at VCC = 2.5 V VCC = 3 V VCC = 3.3 V, Control inputs VCC = 3.6 V, VCC = 3.6 V, VCC = 3.6 V, VCC = 0, VCC = 3.6 V, TEST CONDITIONS II = -18 mA VIN = 0 to 5.5 V VO = 0 to 5.5 V, VI = 0, VO = 0 to 5.5 V, II/O = 0, Switch ON or OFF, Switch OFF, VIN = VCC or GND VI = 0 VIN = VCC or GND Other inputs at VCC or GND 0.3 2.5 5.5 3.5 10.5 VI/O = 5.5 V, 3.3 V, or 0 IO = 30 mA IO = -15 mA IO = 30 mA IO = -15 mA 10.5 4 4 4 4 0.7 MIN TYP MAX -1.8 1 1 1 1.5 30 0.35 3.5 7 5 13 13 8 9 6 8 pF UNIT V A A A mA A mA/ MHz pF pF pF
VCC = 3.6 V, One input at 3 V, VCC = 3.6 V, A and B ports open, Control input switching at 50% duty cycle VCC = 3.3 V, VCC = 3.3 V,
VIN = 5.5 V, 3.3 V, or 0 Switch OFF, VI/O = 5.5 V, 3.3 V, or 0 VIN = VCC or GND, Switch OFF, VIN = VCC or GND, Switch ON, VIN = VCC or GND, VI = 0, VI = 1.7 V, VI = 0, VI = 2.4 V, VI/O = 5.5 V, 3.3 V, or 0
ron#
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see Figure 2). # Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER fOE or fS|| tpdk tpd(s) ten tdis FROM (INPUT) OE or S A or B S S OE S OE TO (OUTPUT) A or B B or A A B A or B B A or B 1.5 1.5 1.5 1 1 VCC = 2.5 V 0.2 V MIN MAX 10 0.12 6.5 6.5 6.5 6 6 1.5 1.5 1.5 1 1 VCC = 3.3 V 0.3 V MIN MAX 20 0.2 5.5 5.5 5.5 6 6 ns MHz ns ns UNIT
ns
|| Maximum switching frequency for control inputs (VO > VCC, VI = 5 V, RL 1 M, CL = 0). k The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
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SCDS135A - SEPTEMBER 2003 - REVISED NOVEMBER 2003
SN74CB3Q3257 4 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER 2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH BUS SWITCH
TYPICAL ron vs VI
16 14 ron - Resistance - W 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 VI - V 3.0 3.5 4.0 4.5 5.0 VCC = 3.3 V TA = 25C , IO = -15 mA
Figure 1. Typical ron vs VI, VCC = 3.3 V and IO = -15 mA
TYPICAL ICC vs CONTROL-INPUT SWITCHING FREQUENCY
12 10 ICC - mA 8 6 4 2 0 0 2 4 6 8 10 12 14 16 18 20 OE or S Switching Frequency - MHz S Switching OE Switching VCC = 3.3 V TA = 25C A and B Ports Open
Figure 2. Typical ICC vs OE or S Switching Frequency, VCC = 3.3 V
6
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SN74CB3Q3257 4 BIT 1 OF 2 FET MULTIPLEXER/DEMULTIPLEXER 2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH BUS SWITCH
SCDS135A - SEPTEMBER 2003 - REVISED NOVEMBER 2003
PARAMETER MEASUREMENT INFORMATION
Input Generator VIN 50 VG1 50 DUT Input Generator 50 VG2 RL RL S1 2 x VCC Open GND 50 CL (see Note A) VCC
TEST CIRCUIT
VI
VO
TEST tpd(s) tPLZ/tPZL tPHZ/tPZH
VCC 2.5 V 0.2 V 3.3 V 0.3 V 2.5 V 0.2 V 3.3 V 0.3 V 2.5 V 0.2 V 3.3 V 0.3 V
S1 Open Open 2 x VCC 2 x VCC GND GND
RL 500 500 500 500 500 500
VI VCC or GND VCC or GND GND GND VCC VCC Output Control (VIN) tPZL
CL 30 pF 50 pF 30 pF 50 pF 30 pF 50 pF
V
0.15 V 0.3 V 0.15 V 0.3 V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 tPZH VOL + V tPHZ VOH - V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL
Output Control (VIN) tPLH Output
VCC VCC/2 VCC/2 0V tPHL VOH VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B)
Output Waveform 2 S1 at GND (see Note B)
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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7
MECHANICAL DATA
MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000
DGV (R-PDSO-G**)
24 PINS SHOWN 0,23 0,13 13
PLASTIC SMALL-OUTLINE
0,40 24
0,07 M
0,16 NOM 4,50 4,30 6,60 6,20
Gage Plane
0,25 0- 8 1 A 12 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,08
PINS ** DIM A MAX A MIN
14 3,70 3,50
16 3,70 3,50
20 5,10 4,90
24 5,10 4,90
38 7,90 7,70
48 9,80 9,60
56 11,40 11,20
4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194
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MECHANICAL DATA
MSOI004E JANUARY 1995 - REVISED MAY 2002
DBQ (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
0.025 (0,64) 24
0.012 (0,30) 0.008 (0,20) 13
0.005 (0,13)
0.157 (3,99) 0.150 (3,81)
0.244 (6,20) 0.228 (5,80)
0.008 (0,20) NOM
Gauge Plane 1 A 0-8 0.069 (1,75) MAX 0.035 (0,89) 0.016 (0,40) 12 0.010 (0,25)
Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
16 0.197 (5,00) 0.189 (4,80)
20 0.344 (8,74) 0.337 (8,56)
24 0.344 (8,74) 0.337 (8,56)
28 0.394 (10,01) 0.386 (9,80)
A MIN
D
M0-137 VARIATION
AB
AD
AE
AF
4073301/F 02/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-137.
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MECHANICAL DATA
MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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